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ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 ddr sdram unbuffered module 184pin unbuffered module based on 256mb e-die with 64/72-bit ecc/non ecc revision 1.1 august. 2003
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 revision history revision 1.0 (april, 2003) - first release revision 1.1 (august, 2003) - corrected typo.
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 samsung electronics co., ltd. reserves the right to change products and specif ications without notice. ordering information operating frequencies part number density organization component composition height m368l3223etn-c(l)b3/aa/a2/b0 256mb 32m x 64 32mx8 (k4h560838e) * 8ea 1,250mil m381l3223etm-c(l)b3/aa/a2/b0 256mb 32m x 72 32mx8 (k4h560838e) * 9ea 1,250mil m368l6423etn-c(l)b3/aa/a2/b0 512mb 64m x 64 32mx8 (k4h560838e) * 16ea 1,250mil m381l6423etm-c(l)b3/aa/a2/b0 512mb 64m x 72 32mx8 (k4h560838e) * 18ea 1,250mil b3(ddr333@cl=2.5) aa(ddr266@cl=2) a2(ddr266@cl=2) b0(ddr266@cl=2.5) speed @cl2 133mhz 133mhz 133mhz 100mhz speed @cl2.5 166mhz 133mhz 133mhz 133mhz cl-trcd-trp 2.5-3-3 2-2-2 2-3-3 2.5-3-3 feature ? power supply : vdd: 2.5v 0.2v, vddq: 2.5v 0.2v ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs tr ansition with ck transition ? programmable read latency 2, 2.5 (clock) ? programmable burst length (2, 4, 8) ? programmable burst type (sequential & interleave) ? edge aligned data output, center aligned data input ? auto & self refresh, 7.8us re fresh interval(8 k/64ms refresh) ? serial presence detect with eeprom ? pcb : height 1,250 (mil), single (256mb), double (512mb) sided 184pin unbuffered dimm based on 256mb e-die (x8,)
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 pin configuration (front side/back side) note : 1. * : these pins are not used in this module. 2. pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72(m381 ~ ) m odule, and are not used on x64(m368 ~ ) module. 3. pins 111, 158 are nc for 1row modules [ m368(81)l32 23etn(m)] & used for 2row modules [m368(81)l6423etn(m) ] . pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vref dq0 vss dq1 dqs0 dq2 vdd dq3 nc nc vss dq8 dq9 dqs1 vddq ck1 /ck1 vss dq10 dq11 cke0 vddq dq16 dq17 dqs2 vss a9 dq18 a7 vddq dq19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 a5 dq24 vss dq25 dqs3 a4 vdd dq26 dq27 a2 vss a1 cb0 cb1 vdd dqs8 a0 cb2 vss cb3 ba1 dq32 vddq dq33 dqs4 dq34 vss ba0 dq35 dq40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 vddq /we dq41 /cas vss dqs5 dq42 dq43 vdd */cs2 dq48 dq49 vss /ck2 ck2 vddq dqs6 dq50 dq51 vss vddid dq56 dq57 vdd dqs7 dq58 dq59 vss nc sda scl 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 vss dq4 dq5 vddq dm0 dq6 dq7 vss nc nc nc vddq dq12 dq13 dm1 vdd dq14 dq15 cke1 vddq *ba2 dq20 a12 vss dq21 a11 dm2 vdd dq22 a8 dq23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 vss a6 dq28 dq29 vddq dm3 a3 dq30 vss dq31 cb4 cb5 vddq ck0 /ck0 vss dm8 a10 cb6 vddq cb7 vss dq36 dq37 vdd dm4 dq38 dq39 vss dq44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 /ras dq45 vddq /cs0 /cs1 dm5 vss dq46 dq47 */cs3 vddq dq52 dq53 *a13 vdd dm6 dq54 dq55 vddq nc dq60 dq61 vss dm7 dq62 dq63 vddq sa0 sa1 sa2 vddspd key key pin description pin name function pin name function a0 ~ a12 address input (multiplexed) dm0 ~ 7, 8(for ecc) data - in mask ba0 ~ ba1 bank select address vdd power supply (2.5v) dq0 ~ dq63 data input/output vdd q power supply for dqs(2.5v) dqs0 ~ dqs8 data stro be input/output vss ground ck0,ck0 ~ ck2, ck2 clock input vref power supply for reference cke0, cke1(for double banks) clock enable input vddspd serial eeprom power/supply ( 2.3v to 3.6v ) cs0 , cs1 (for double banks) chip select input sda serial data i/o ras row address strobe scl serial clock cas column address strobe sa0 ~ 2 address in eeprom we write enable nc no connection cb0 ~ cb7 (for x72 module) check bit(data-in/data-out)
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 cs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 256mb, 32m x 64 non ecc mo dule (m368l3223etn) (populated as 1 bank of x8 ddr sdram module) functional block diagram a0 - a12 a0-a12 : ddr sdrams d0 - d7 ras ras : ddr sdrams d0 - d7 cas cas : ddr sdrams d0 - d7 we we : ddr sdrams d0 - d7 cke0 cke : ddr sdrams d0 - d7 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d7 v ss d0 - d7 v dd /v ddq d0 - d7 d0 - d7 vref v ddspd spd d0 - d7 *clock net wiring * clock wiring clock input ddr sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 3 ddr sdrams 3 ddr sdrams 2 ddr sdrams card edge d3/d0/d6 cap/cap/cap d4/d1/d7 cap/cap/cap d5/d2/cap cap/cap/cap r=120 ? ck0/1/2 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 5.1 ohms + 5% ck0/1/2
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 256mb, 32m x 72 ecc module (m381l3223etm) (populated as 1 bank of x8 ddr sdram module) functional block diagram a0 - a12 a0-a12 : ddr sdrams d0 - d8 ras ras : ddr sdrams d0 - d8 cas cas : ddr sdrams d0 - d8 we we : ddr sdrams d0 - d8 cke0 cke : ddr sdrams d0 - d8 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d8 v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 vref v ddspd spd d0 - d8 *clock net wiring * clock wiring clock input ddr sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 3 ddr sdrams 3 ddr sdrams 3 ddr sdrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp cs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dqs8 dm8 dm/ cs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 d8 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 card edge d3/d0/d6 cap/cap/cap d4/d1/d7 cap/cap/cap d5/d2/d8 cap/cap/cap r=120 ? ck0/1/2 ck0/1/2 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 5.1 ohms + 5%
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 512mb, 64m x 64 non ecc module (m368l6423etn) (populated as 2 bank of x8 ddr sdram module) functional block diagram cs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dm/ cs dqs d8 dm/ cs dqs d9 dm/ cs dqs d10 dm/ cs dqs d11 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm/ cs dqs d12 dm/ cs dqs d13 dm/ cs dqs d14 dm/ cs dqs d15 cs 1 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 a0 - a12 a0-a12: ddr sdrams d0 - d15 ras ras : ddr sdrams d0 - d15 cas cas : ddr sdrams d0 - d15 we we : ddr sdrams d0 - d15 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d15 v ss d0 - d15 v dd /v ddq d0 - d15 d0 - d15 vref v ddspd spd d0 - d15 *clock net wiring * clock wiring clock input ddr sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 4 ddr sdrams 6 ddr sdrams 6 ddr sdrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp card edge d3/d0/d5 d11/d8/d13 cap/d1/d6 cap/d9/d14 d4/d2/d7 d12/d10/d15 r=120 ? ck0/1/2 * * cke 0/1 cke : ddr sdrams d0 - d15 ck0/1/2 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 3 ohms + 5%
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 512mb, 64m x 72 ecc module (m381l6423etm) (populated as 2 bank of x8 ddr sdram module) functional block diagram cs 0 dqs0 dm0 dm/ cs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dqs1 dm1 dm/ cs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d1 dqs 2 dm2 dm/ cs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d2 dqs3 dm3 dm/ cs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 d3 dqs4 dm4 dm/ cs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d4 dqs5 dm5 dm/ cs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 d5 dqs6 dm6 dm/ cs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dqs7 dm7 dm/ cs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dm/ cs dqs d9 dm/ cs dqs d10 dm/ cs dqs d11 dm/ cs dqs d12 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm/ cs dqs d13 dm/ cs dqs d14 dm/ cs dqs d15 dm/ cs dqs d16 cs 1 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 a0 - a12 a0-a12 : ddr sdrams d0 - d17 ras ras : ddr sdrams d0 - d17 cas cas : ddr sdrams d0 - d17 we we : ddr sdrams d0 - d17 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d17 v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd d0 - d17 *clock net wiring * clock wiring clock input ddr sdrams *ck0/ck0 *ck1/ck1 *ck2/ck2 6 ddr sdrams 6 ddr sdrams 6 ddr sdrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp cke0/1 cke : ddr sdrams d0 - d17 dqs8 dm8 dm/ cs dqs d8 i/o 7 i/o 6 i/o 1 i/o 0 i/o 5 i/o 4 i/o 3 i/o 2 dm/ cs dqs d17 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors:3 ohms + 5% card edge d3/d0/d5 d12/d9/d14 d8/d1/d6 d17/d10/d15 d4/d2/d7 d13/d11/d16 r=120 ? ck0/1/2 ck0/1/2
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd & v ddq supply relative to v ss v dd , v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.5 * # of component w short circuit current i os 50 ma note : permanent device damage may occur if ab solute maximum ratings are exceeded. functional operation should be restricted to recommend operation condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. dc operating conditions recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.3 2.7 i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.36 v ddq +0.6 v 3 v-i matching: pullup to pulldown current ratio vi(ratio) 0.71 1.4 - 4 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(norma l strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(norma l strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9ma 1.vref is expected to be equal to 0.5*vddq of the transmitti ng device, and to track variations in the dc level of same. peak-to peak noise on vref may not exceed +/-2% of the dc value. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between t he input level on ck and the input level on ck . 4. the ratio of the pullup current to th e pulldown current is specified for the sa me temperature and volt age, over the entire temperature and voltage range, for device drain to source voltages from 0.25 v to 1.0v. for a given output, it represents t he maximum difference between pullup and pulldown drivers due to process variation. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to so urce voltages from 0.1 to 1.0. note :
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol b3(ddr333@cl=2.5) aa(ddr266@cl=2) a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 720 720 640 640 ma idd1 920 920 840 840 ma idd2p24242424ma idd2f 200 160 160 160 ma idd2q 160 150 150 150 ma idd3p 280 240 240 240 ma idd3n 440 360 360 360 ma idd4r 1,280 1,120 1,120 1,120 ma idd4w 1,280 1,080 1,080 1,080 ma idd5 1,360 1,280 1,280 1,280 ma idd6 normal 24 24 24 24 ma low power 12 12 12 12 ma optional idd7a 2,240 2,240 2,000 2,000 ma ddr sdram idd spec table m368l3223etn [ (32m x 8) * 8, 256mb non ecc module ] (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol b3(ddr333@cl=2.5) aa(ddr266@cl=2) a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 810 810 720 720 ma idd1 1,040 1,040 950 950 ma idd2p27272727ma idd2f 230 180 180 180 ma idd2q 180 170 170 170 ma idd3p 320 270 270 270 ma idd3n 500 410 410 410 ma idd4r 1,440 1260 1260 1,260 ma idd4w 1,440 1,220 1,220 1,220 ma idd5 1,530 1,440 1,440 1,440 ma idd6 normal 27 27 27 27 ma low power 14 14 14 14 ma optional idd7a 2,520 2,520 2,250 2,250 ma m381l3223etm [ (32m x 8) * 9, 256mb ecc module ]
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol b3(ddr333@cl=2.5) aa(ddr266@cl=2) a2(ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 1,160 1,160 1,000 1,000 ma idd1 1,360 1,360 1,200 1,200 ma idd2p 48 48 48 48 ma idd2f 400 320 320 320 ma idd2q 320 290 290 290 ma idd3p 560 480 480 480 ma idd3n 880 720 720 720 ma idd4r 1,720 1,480 1,480 1,480 ma idd4w 1,720 1,440 1,440 1,440 ma idd5 1,800 1,640 1,640 1,640 ma idd6 normal 48 48 48 48 ma low power 24 24 24 24 ma optional idd7a 2,680 2,680 2,360 2,360 ma ddr sdram idd spec table m368l6423etn [ (32m x 8) * 16, 512mb non ecc module ] (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol b3(ddr333@cl=2.5) aa(ddr266@cl=2) a2 (ddr266@cl=2) b0(ddr266@cl=2.5) unit notes idd0 1,310 1,310 1,130 1,130 ma idd1 1,530 1,530 1,350 1,350 ma idd2p 54 54 54 54 ma idd2f 450 360 360 360 ma idd2q 360 330 330 330 ma idd3p 630 540 540 540 ma idd3n 990 810 810 810 ma idd4r 1,940 1,670 1,670 1,670 ma idd4w 1,940 1,620 1,620 1,620 ma idd5 2,030 1,850 1,850 1,850 ma idd6 normal 54 54 54 54 ma low power 27 27 27 27 ma optional idd7a 3,020 3,020 2,660 2,660 ma m381l6423etm [ (32m x 8) * 18, 512mb ecc module ]
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 note : 1. vid is the magnitude of the difference bet ween the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same. 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specif icatims are refation to a vref envelope that has been bandwidth limited 20mhz. output load circuit (sstl_2) output z0=50 ? c load =30pf v ref =0.5*v ddq r t =50 ? v tt =0.5*v ddq input/output capacitance (vdd=2.5v, vddq=2.5v, ta= 25 c, f=1mhz) parameter symbol m368l3223etn m381l3223etm unit min max min max input capacitance(a0 ~ a12, ba0 ~ ba1,ras ,cas ,we )cin149575160pf input capacitance(cke0) cin2 42 50 44 53 pf input capacitance( cs 0) cin3 42 50 44 53 pf input capacitance( clk0, clk1,clk2) cin4 25 30 25 30 pf input capacitance(dm0~dm7, dm8(for ecc)) cin5 6767pf data & dqs input/output capacitance(dq0~dq63)cout16767pf data input/output capacitance (cb0~cb7) cout2 - - 6 7 pf parameter symbol m368l6423etn m381l6423etm unit min max min max input capacitance(a0 ~ a12, ba0 ~ ba1,ras ,cas ,we )cin165816987pf input capacitance(cke0,cke1) cin2 42 50 44 53 pf input capacitance( cs 0, cs 1) cin3 42 50 44 53 pf input capacitance( clk0, clk1,clk2) cin4 28 34 28 34 pf input capacitance(dm0~dm7, dm8(for ecc)) cin5 10 12 10 12 pf data & dqs input/output capacitance(dq0~dq63) cout1 10 12 10 12 pf data input/output capacitance (cb0~cb7) cout2 - - 10 12 pf ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.31 v 3 input low (logic 0) voltage, dq, dq s and dm signals. vil(ac) vref - 0.31 v 3 input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 ac timming parameters & specifications parameter symbol b3 (ddr333@cl=2.5) aa (ddr266@cl=2.0 a2 (ddr266@cl=2.0) b0 (ddr266@cl=2.5) unit note min max min max min max row cycle time trc 60 60 65 65 ns refresh row cycle time trfc 72 75 75 75 ns row active time tras 42 70k 45 120k 45 120k 45 120k ns ras to cas delay trcd 18 15 20 20 ns row precharge time trp 18 15 20 20 ns row active to row active delay trrd 12 15 15 15 ns write recovery time twr 15 15 15 15 ns last data in to read command twtr 1 1 1 1 tck col. address to col. address delay tccd 1 1 1 1 tck clock cycle time cl=2.0 tck 7.5 12 7.5 12 7.5 12 10 12 ns cl=2.5 6 12 7.5 12 7.5 12 7.5 12 ns clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ck tdqsck -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns output data access time from ck/ck tac -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns data strobe edge to ouput data edge tdqsq - 0.45 - 0.5 - 0.5 - 0.5 ns 12 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 0 ns 3 dqs-in hold time twpre 0.25 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 0.35 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control input setup time(fast) tis 0.75 0.9 0.9 0.9 ns i,5.7~9 address and control input hold time(fast) tih 0.75 0.9 0.9 0.9 ns i,5.7~9 address and control input setup time(slow) tis 0.8 1.0 1.0 1.0 ns i, 6~9 address and control input hold time(slow) tih 0.8 1.0 1.0 1.0 ns i, 6~9 data-out high impedence time from ck/ck thz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns 1 data-out low impedence time from ck/ck tlz -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns 1 input slew rate(for input only pins) tsl(i) 0.5 0.5 0.5 0.5 v/ns input slew rate(for i/o pins) tsl(io) 0.5 0.5 0.5 0.5 v/ns output slew rate(x4,x8) tsl(o) 1.0 4.5 1.0 4.5 1.0 4.5 1.0 4.5 v/ns output slew rate matching ratio(rise to fall) tslmr 0.67 1.5 0.67 1.5 0.67 1.5 0.67 1.5
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 parameter symbol b3 (ddr333@cl=2.5)) aa (ddr266@cl=2.0) a2 (ddr266@cl=2.0) b0 (ddr266@cl=2.5)) unit note min max min max min max mode register set cycle time tmrd 12 15 15 15 ns dq & dm setup time to dqs tds 0.45 0.5 0.5 0.5 ns j, k dq & dm hold time to dqs tdh 0.45 0.5 0.5 0.5 ns j, k control & address input pulse width tipw 2.2 2.2 2.2 2.2 ns 8 dq & dm input pulse width tdipw 1.75 1.75 1.75 1.75 ns 8 power down exit time tpdex 6 7.5 7.5 7.5 ns exit self refresh to non-read command txsnr 75 75 75 75 ns exit self refresh to read command txsrd 200 200 200 200 tck refresh interval time trefi 7.8 7.8 7.8 7.8 us 4 output dqs valid window tqh thp -tqhs - thp -tqhs - thp -tqhs - thp -tqhs -ns11 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - ns 10, 11 data hold skew factor tqhs 0.55 0.75 0.75 0.75 ns 11 dqs write postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tck 2 active to read with auto precharge command trap 18 20 20 20 autoprecharge write recovery + precharge time tdal (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) (twr/tck) + (trp/tck) tck 13 system characteristics for ddr sdram the following specification parameters are required in systems using ddr333& ddr266 devices to ensure proper system performance. these charac teristics are for system simulation purposes and are guaranteed by design. table 1 : input slew rate for dq, dqs, and dm table 2 : input setup & hold time derating for slew rate table 3 : input/output setup & ho ld time derating for slew rate ac characteristics ddr333 ddr266 parameter symbol min max min max units notes dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew tbd tbd tbd tbd v/ns a, m input slew rate tis tih units notes 0.5 v/ns 0 0 ps i 0.4 v/ns +50 0 ps i 0.3 v/ns +100 0 ps i input slew rate tds tdh units notes 0.5 v/ns 0 0 ps k 0.4 v/ns +75 +75 ps k 0.3 v/ns +150 +150 ps k
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 table 4 : input/output setup & hold de rating for rise/fall delta slew rate table 5 : output slew rate char acteristice (x4, x8 devices only) table 6 : output slew rate ch aracteristice (x16 devices only) table 7 : output slew rate matching ratio characteristics delta slew rate tds tdh units notes +/- 0.0 v/ns 0 0 ps j +/- 0.25 v/ns +50 +50 ps j +/- 0.5 v/ns +100 +100 ps j slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h ac characteristics ddr333 ddr266 parameter min max min max notes output slew rate matching ratio (pullup to pulldown) tbd tbd tbd tbd e,m
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 component notes 1. thz and tlz transitions occur in the same access time wi ndows as valid data transitions. these parameters are not referenc ed to a specific voltage level but specify when the device output in no longer driving (hz), or begins driving (lz). 2. the maximum limit for this parameter is not a device limi t. the device will operate with a greater value for this paramete r, but sys tem performance (bus turnaround) will degrade accordingly. 3. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this ck edg e. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes we re previ ously in progress on the bus, dqs will be tran sitioning from high- z to logic low. if a previous write wa s in progress , dqs could be high, low, or transit ioning from high to low at th is time, depending on tdqss. 4. a maximum of eight auto refresh comman ds can be posted to any given ddr sdram device. 5. for command/address input slew rate 1.0 v/ns 6. for command/address input slew rate 0.5 v/ns and < 1.0 v/ns 7. for ck & ck slew rate 1.0 v/ns 8. these parameters guarantee device ti ming, but they are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. 9. slew rate is measur ed between voh(ac) and vol(ac). 10. min (tcl, tch) refers to the smaller of the actual clock low time and t he actual clock high time as provided to the device (i.e. this value can be greater than the mini mum specification limits for tcl and tch)..... for example, tcl and tch are = 50% of th e period, less the half period jitt er (tjit(hp)) of the clock source, and less the half period jitter due to crosstalk (tji t(crosstalk)) into the clock traces. 11. tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defined by cl ock high or clock low (tch , tcl). tqhs accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one tansition followed by the worst case pull-in of dq on the next transition, both of wh ich are, separately, due to data pin skew and output pattern effect s, and p- channel to n-channel variation of the output drivers. 12. tdqsq consists of data pin skew and output pattern effect s, and p-channel to n-channel vari ation of the outpu t drivers for any given cycle. 13. tdal = (twr/tck) + (trp/tck) for each of the terms above, if not already an integer, round to the next highest integer. example: for ddr266b at cl=2.5 and tck=7.5ns tdal = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tdal = 5 clocks
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 system notes : a. pullup slew rate is characteristized under the test conditions as shown in figure 1. output test point vssq 50 ? figure 1 : pullup slew rate test load b. pulldown slew rate is measured under the test conditions shown in figure 2. output test point vddq 50 ? figure 2 : pulldown slew rate test load c. pullup slew rate is measured between (vddq/2 - 320 mv +/- 250 mv) pulldown slew rate is measured between (vddq/2 + 320 mv +/- 250 mv) pullup and pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only on e output switching. example : for typical slew rate, dq0 is switching for minmum slew rate, all dq bits are switching from either high to low, or low to high. the remaining dq bits remain the same as for previous state. d. evaluation conditions typical : 25 c (t ambient), vddq = 2.5v, typical process minimum : 70 c (t ambient), vddq = 2. 3v, slow - slow process maximum : 0 c (t ambient), vddq = 2.7v, fast - fast process e. the ratio of pullup slew rate to pulldown slew rate is specif ied for the same temperature and voltage, over the entire tempe rature and voltage range. for a given output, it represents the maxi mum difference between pullup and pulldown drivers due to process variation. f. verified under typical condit ions for qualification purposes. g. tsopii package divices only. h. only intended for operation up to 266 mbps per pin. i. a derating factor will be used to increase tis and tih in the case where the input slew rate is below 0.5v/ns as shown in table 2. the input slew rate is based on the lesse r of the slew rates detemined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), si milarly for rising transitions. j. a derating factor will be used to increas e tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tabl es 3 & 4. input slew rate is based on the larger of ac-ac delta rise , fall rate and dc-dc delta rise, input slew rate is based on the lesser of the slew rates determined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example : if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is - 0.5ns/v . using the table given, this would result in the need for an increase in tds and tdh of 100 ps. k. table 3 is used to increase tds and tdh in the case where the i/ o slew rate is below 0.5 v/ns. the i/o slew rate is based on the lesser on the lesser of the ac - ac slew rate and the dc- dc slew rate. the inut slew rate is based on the lesser of the slew rate s deter mined by either vih(ac) to vil(ac) or vih( dc) to vil(dc), and similarly for rising transitions. m. dqs, dm, and dq input slew rate is sp ecified to prevent double clocking of data and preserve setup and hold times. signal tr ansi tions through the dc region must be monotony.
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba0,1 a10/ap a0 ~ a9 a11, a12 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll lh x 3 self refresh entry l 3 exit l h lh hh x 3 hx x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable hxlhlhv l column address 4 auto precharge enable h 4 write & column address auto precharge disable hxlhllv l column address 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lv vv exit l h x x x x precharge power down mode entry h l hx x x x lh hh exit l h hx x x lv vv dm h x x 8 no operation (nop) : not defined h x hx x x x 9 lh hh 9 note : 1. op code : operand code. a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functi ons are same as the cbr refresh of dram. the automatical precharg e without row precharge co mmand is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row acti ve and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/writ e command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop co mmand is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at t he both edges (write dm latency i s 0). 9. this combination is not defined for any function, which means "no op eration(nop)" in ddr sdram.
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 tolerances : 0.005(.13) unless ot herwise specified. the used device is 32mx8 ddr sdram, tsopii. ddr sdram part no : k4h560838e-t*** 5.25 0.006 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.100 min (2.30 min) 0.393 (10.00) (1.270) 0.100 (2.50 ) detail b a b (128.950) (133.350 0.15) 0.250 (6.350) detail a 0.157 (4.00) 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (6.62) (64.77) (49.53) (17.80) 2.55 1.95 0.26 2.500 0.7 0.10 m c ba 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 1.25 0.006 (31.75 0.15) (4.00) (2x) 0.157 0.10 m c a m b (3.00) 0.118 physical dimensions : 32mx64 (m368l3223etn) 0.07 max 0.050 0.0039 (1.270 0.10) (1.20 max)
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 tolerances : 0.005(.13) unless ot herwise specified. the used device is 32mx8 ddr sdram, tsopii. ddr sdram part no : k4h560838e-t*** 5.25 0.006 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.100 min (2.30 min) 0.393 (10.00) (1.270) 0.100 (2.50 ) detail b a b (128.950) (133.350 0.15) 0.250 (6.350) detail a 0.157 (4.00) 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (6.62) (64.77) (49.53) (17.80) 2.55 1.95 0.26 2.500 0.7 0.10 m c ba 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 1.25 0.006 (31.75 0.15) (4.00) (2x) 0.157 0.10 m c a m b (3.00) 0.118 physical dimensions : 32mx72 (m381l3223etm) 0.07 max 0.050 0.0039 (1.270 0.10) (1.20 max)
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 tolerances : 0.005(.13) unless ot herwise specified. the used device is 32mx8 ddr sdram, tsopii. ddr sdram part no : k4h560838e-t*** 5.25 0.006 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.145 max 0.050 0.0039 (1.270 0.10) 0.100 min (2.30 min) 0.393 (10.00) (1.270) 0.100 (2.50 ) detail b a b (128.950) (133.350 0.15) 0.250 (6.350) detail a 0.157 (4.00) 0.071 (1.80) (3.67 max) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (6.62) (64.77) (49.53) (17.80) 2.55 1.95 0.26 2.500 0.7 0.10 m c ba 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 1.25 0.006 (31.75 0.15) (4.00) (2x) 0.157 0.10 m c a m b (3.00) 0.118 physical dimensions : 64mx64 (m368l6423etn)
ddr sdram 256mb, 512mb unbuffered dimm rev. 1.1 august. 2003 tolerances : 0.005(.13) unless ot herwise specified. the used device is 32mx8 ddr sdram, tsopii. ddr sdram part no : k4h560838e-t*** 5.25 0.006 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.145 max 0.050 0.0039 (1.270 0.10) 0.100 min (2.30 min) 0.393 (10.00) (1.270) 0.100 (2.50 ) detail b a b (128.950) (133.350 0.15) 0.250 (6.350) detail a 0.157 (4.00) 0.071 (1.80) (3.67 max) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (6.62) (64.77) (49.53) (17.80) 2.55 1.95 0.26 2.500 0.7 0.10 m c ba 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 1.25 0.006 (31.75 0.15) (4.00) (2x) 0.157 0.10 m c a m b (3.00) 0.118 physical dimensions : 64mx72 (m381l6423etm)

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